1. Technical Field
The present invention relates generally to a semiconductor memory apparatus, and more particularly to a semiconductor memory apparatus including a bit line sense amplifier.
2. Related Art
A bit line sense amplifier used in a semiconductor memory apparatus senses and amplifies data stored in a memory cell. The bit line sense amplifier is coupled to a bit line pair including a bit line BL connected to the memory cell, and amplifies the voltage level of data detected from the bit line BL with which the charge of memory cell is shared.
FIG. 1 illustrates a known bit line sense amplifier. Referring to FIG. 1, the bit line sense amplifier includes two pairs of inverters N1, P1, N2, and P2 forming a latch structure between a bit line pair BL and BLB. Such a bit line sense amplifier serves to amplify the voltage level of data detected from the bit line BL with which the charge of memory cell is shared.
During a sensing operation, as levels of bit line sense amplifier driving signals, which have been maintaining predetermined precharge voltage levels, changes, e.g., as levels of a power driving signal RTO (e.g., core voltage level) and a ground driving signal SB (e.g., ground voltage level), each of which has been maintaining VCORE/2, is transitioned to a high voltage and a low voltage, respectively, the bit line sense amplifier performs a sensing operation. The voltage level of the bit line BLT is transitioned to a core voltage level Vcore (or a ground voltage level VSS) and the voltage level of the bit line bar BLB is transitioned to the ground voltage level VSS (or the core voltage level Vcore).
However, in the above-described known bit line sense amplifier, a low voltage characteristic may be deteriorated due to a high threshold voltage of a MOS transistor forming the bit line sense amplifier. Furthermore, if the threshold voltage is reduced so as to improve the low voltage characteristic, a leakage current may increase. Therefore, there is a limit in reducing the threshold voltage.
FIG. 2 is a circuit diagram of a bit line sense amplifier which includes an additional sense amplification unit having a low threshold voltage.
The bit line sense amplifier illustrated in FIG. 2, which has been developed to improve a low voltage characteristic, further includes the additional sense amplification unit having a lower threshold voltage than the sense amplifier illustrated in FIG. 1.
The bit line sense amplifier of FIG. 2 includes a first sense amplification unit 10 and a second sense amplification unit 20.
The first sense amplification unit 10 may include the sense amplifier illustrated in FIG. 1. The first sense amplification unit 10 is driven to a voltage level of a power driving signal RTO and a ground driving signal SB, and includes first inverters N1 and P1 and second inverters N2 and P2 forming a latch structure between a bit line BL and a bit line bar BLB.
When a word line (not illustrated) is enabled, the bit line BL shares the charge stored in a memory cell (not illustrated). Also, bit line sense amplifier driving signals, e.g., the power driving signal RTO and the ground driving signal SB maintain predetermined precharge voltage levels (e.g., VCORE/2). When the word line is enabled, the power driving signal RTO and the ground driving signal SB is transitioned to a core voltage level and a ground voltage level, respectively.
Then, the bit line sense amplifier performs a sensing operation. The bit line sense amplifier senses a voltage difference between the bit line pair BL and BLB, If there is a voltage difference, the bit line sense amplifier pulls the bit line BL up to the core voltage level (or the ground voltage level) and pulls the bit line bar BLB down to the ground voltage level (or the core voltage level).
However, in order for the bit line sense amplifier to perform a sensing operation, the voltage level corresponding to the charge shared by the bit line pair BL and BLB, e.g., the voltage level corresponding to the charge shared by the bit line BL should be higher than the threshold voltage of the transistors N1, P1, N2, and P2.
The second sense amplification unit 20 includes a sense amplifier having a lower threshold voltage than the transistors N1, P1, N2, and P2 used in the first sense amplifier 10. The second sense amplification unit 20 includes a transistor pair N5 and N6 forming, for example, a latch structure between the bit line BL and the bit line bar BLB and activated in response to an activated switching signal SG.
The transistor pair includes fifth and sixth NMOS transistors N5 and N6 having a gate terminal connected to the bit line BL or the bit line bar BLB, a drain terminal connected to the other bit line, and a source terminal connected to a ground voltage VSS.
The above-described transistor pair N5 and N6 forming, for example, a latch structure may change a low level of data of the bit line BL or the bit line bar BLB to the ground voltage level, thereby amplifying the data. For example, when high-level data is loaded on the bit line BL, the fifth NMOS transistor N5 is turned on to pull the bit line bar BLB down to the ground voltage level VSS. On the other hand, when high-level data is loaded on the bit line bar BLB, the sixth NMOS transistor N6 is turned on to pull the bit line BL down to the ground voltage level VSS.
Since the fifth and sixth NMOS transistors N5 and N6 have a low threshold voltage, a leakage current may increase. Therefore, the second sense amplification unit 20 may further include a voltage passing section 21 between the bit line pair BL and BLB and the fifth and sixth NMOS transistors N5 and N6. The voltage passing section 21 is configured to connect the bit line pair BL and BLB to the fifth and sixth NMOS transistors N5 and N6 in response to a switching signal SG.
The switching signal SG is activated when an amplification operation for the data shared by the bit line is requested. For example, the switching signal SG may be activated when an active signal is inputted to perform a bit line sensing operation, a read operation, or a write operation.
The voltage passing section 21 may include third and fourth NMOS transistors N3 and N4. The third NMOS transistor N3 is configured to connect the bit line bar BLB and a drain terminal of the fifth NMOS transistor N5 in response to the switching signal SG, and the fourth NMOS transistor N4 is configured to connect the bit line BL and a drain terminal of the sixth NMOS transistor N6 in response to the switching signal SG. That is, the voltage passing section 21 may control the second sense amplification unit 20 to perform a sensing operation only at a specific time.
That is, since the second sense amplification unit 20 is enabled by the voltage passing unit 21 only when data sensing is necessary, it is possible to block a leakage current caused by a low threshold voltage to a predetermined extent.
However, since the fifth and sixth NMOS transistors N5 and N6 of the second sense amplification unit 20 are connected to the ground voltage VSS, a leakage current in a standby state may occur in a path where the third and fifth NMOS transistors N3 and N5 are connected to or the fourth and sixth NMOS transistors N4 and N6 are connected to the bit line pair BL and BLB which have been precharged to the precharge voltage (for example, VCORE/2).